Rectifier circuit and electronic device

ABSTRACT

A rectifier circuit including a switch element, controls connection and disconnection of an AC input voltage using the switch element to generate an output voltage. The switch element includes an n-channel MOS transistor. The rectifier circuit further includes a booster circuit and a control signal generation unit, and establishes connection to the switch element at a peak portion of the input voltage. The booster circuit is configured to generate and apply a gate control signal including a voltage higher than a threshold voltage of the n-channel MOS transistor to a gate of the n-channel MOS transistor. The control signal generation unit is configured to generate and output a control signal for controlling connection and disconnection of the n-channel MOS transistor to the booster circuit.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority of theprior Japanese Patent Application No. 2017-064664, filed on Mar. 29,2017, the entire contents of which are incorporated herein by reference.

FIELD

The embodiments described herein are related to a rectifier circuit andan electronic device.

BACKGROUND

In recent years, the importance of rectifier circuits which operate atlow voltages is increasing. For example, radio frequency identification(RFID) tags or noncontact IC cards include no batteries and extractpower from radio waves (e.g., 13.56-MHz carrier waves) emitted byreaders (readers-writers). In electronic devices, as typified by suchRFID tags, which extract power from radio waves and operate, P-Njunction (PN) diodes or metal-oxide-semiconductor (MOS) transistors aregenerally used as rectifier circuits.

In, e.g., a rectifier circuit implemented in a diode-connected MOStransistor, when the voltage (Vgs) between the gate and the source ofthe transistor is higher than the threshold voltage (Vth) of thetransistor, the transistor is turned on and a current flows from thedrain to the source. When the voltage between the gate and the source islower than the threshold voltage of the transistor, the transistor isturned off and no current flows. In the diode, a current flows when theanode voltage becomes greater than the cathode voltage by a forwardvoltage (Vf) or more.

As described earlier, in the rectifier circuit, a threshold voltageexists at which a switch (a transistor or a diode) is connected anddisconnected (turned on/off), so conduction loss occurs uponrectification. The conduction loss may be improved by reducing thethreshold voltage.

To reduce the threshold voltage, a shot key diode having a low forwardvoltage is used as the aforementioned diode, and a MOS transistor havinga low threshold voltage is used as the aforementioned MOS transistor.However, the manufacture of, e.g., a MOS transistor having a lowthreshold voltage results in the addition of another process(manufacturing process), thus raising the manufacturing cost.

By the way, in the past, various proposals have been made for rectifiercircuits which operate at low voltages.

Patent Document 1: Japanese Laid-open Patent Publication No. 2001-504676

Patent Document 2: Japanese Laid-open Patent Publication No.H03(1991)-218264

Patent Document 3: Japanese Laid-open Patent Publication No. 2008-085818

Patent Document 4: Japanese Laid-open Patent Publication No. 2006-101670

SUMMARY

According to an aspect of the embodiments, there is provided a rectifiercircuit including a switch element, controls connection anddisconnection of an AC input voltage using the switch element togenerate an output voltage. The switch element includes an n-channel MOStransistor.

The rectifier circuit further includes a booster circuit and a controlsignal generation unit, and establishes connection to the switch elementat a peak portion of the input voltage. The booster circuit isconfigured to generate and apply a gate control signal including avoltage higher than a threshold voltage of the n-channel MOS transistorto a gate of the n-channel MOS transistor. The control signal generationunit is configured to generate and output a control signal forcontrolling connection and disconnection of the n-channel MOS transistorto the booster circuit.

The object and advantages of the invention will be realized and attainedby means of the elements and combinations particularly pointed out inthe claims.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary and explanatory and arenot restrictive of the invention.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a diagram for explaining one exemplary rectifier circuit;

FIG. 2A and FIG. 2B are diagrams for explaining another exemplaryrectifier circuit;

FIG. 3 is a block diagram illustrating one embodiment of a rectifiercircuit;

FIG. 4 is a timing chart for explaining the operation of the rectifiercircuit illustrated in FIG. 3;

FIG. 5 is a diagram illustrating in close-up a part of the timing chartillustrated in FIG. 4, to explain it in detail;

FIG. 6 is a block diagram illustrating one exemplary digital timer inthe rectifier circuit illustrated in FIG. 3;

FIG. 7 is a timing chart for explaining the operation of the digitaltimer illustrated in FIG. 6;

FIG. 8 is a circuit diagram illustrating one exemplary reference voltagegenerator in the rectifier circuit illustrated in FIG. 3;

FIG. 9A and FIG. 9B are diagrams for explaining the operation of acomparator based on the output of the reference voltage generatorillustrated in FIG. 8;

FIG. 10 is a circuit diagram illustrating one exemplary timing controlcircuit in the rectifier circuit illustrated in FIG. 3; and

FIG. 11 is a block diagram illustrating one exemplary electronic deviceto which one embodiment of a rectifier circuit is applied.

DESCRIPTION OF EMBODIMENTS

First, before describing embodiments of a rectifier circuit and anelectronic device, exemplary rectifier circuits and their problem willbe described first with reference to FIG. 1, FIG. 2A and FIG. 2B. FIG. 1is a diagram for explaining one exemplary rectifier circuit, and forexplaining a rectifier circuit 200 implemented in a diode-connectedp-channel MOS (pMOS) transistor M0.

As illustrated in FIG. 1, in, e.g., the rectifier circuit 200implemented in the diode-connected pMOS transistor M0, when the voltageVgs between the gate and the source of the transistor M0 is higher thanthe threshold voltage Vth of the transistor, the transistor M0 is turnedon. In other words, the transistor M0 is turned on when the sourcevoltage Va (input voltage Vin) becomes higher than the gate voltage(drain voltage Vb: output voltage Vout′) by the threshold voltage Vth,and a current flows from the drain to the source.

When the voltage Vgs between the gate and the source is lower than thethreshold voltage Vth, the transistor M0 is turned off and no currentflows. In the diode, a current flows when the anode voltage becomesgreater than the cathode voltage by a forward voltage (Vf) or more. Theinput voltage Vin is a signal obtained by receiving via an antenna(coil), radio waves applied from, e.g., a reader to, e.g., an RFID tagor a noncontact IC card equipped with the rectifier circuit 200.

FIG. 2A and FIG. 2B are diagrams for explaining another exemplaryrectifier circuit, in which FIG. 2A illustrates another exemplaryrectifier circuit and FIG. 2B illustrates one exemplary thresholdvoltage generator in the rectifier circuit illustrated in FIG. 2A inmore detail. Another exemplary rectifier circuit 300 includes, e.g., athreshold voltage generator 10 placed between the gate (node N3) and thedrain (node N1) of a pMOS transistor M1, as illustrated in FIG. 2A.

The threshold voltage generator 10 includes a diode-connected pMOStransistor M2, a resistor R1, and a capacitor C10, as illustrated inFIG. 2B. The transistor M2 and the resistor R1 are connected in seriesbetween the nodes N1 and N4, and the two ends of the capacitor C10 areconnected to the nodes N1 and N4. The capacitor C10 is used to maintain(smooth) the rectified drain voltage Vb of the transistor M1 constant.

With this arrangement, a voltage close to a threshold with reference tothe voltage Vb of the drain (node N1) of the transistor M1 may beapplied to the gate (node N3) of the transistor M1 to reduce thethreshold voltage (Vthp1) at which a current starts to flow between thesource and the drain. In other words, conduction loss upon rectificationis reduced by lowering the threshold voltage without adding anotherprocess (without any rise in manufacturing cost due to the addition ofanother manufacturing process). The rectifier circuit illustrated inFIG. 2B may be formed as one semiconductor integrated circuit.

The transistors M1 and M2 are formed (manufactured) by adjusting theirgate lengths and gate widths so that the threshold voltage Vthp1 of thetransistor M1 is slightly greater (greater by a voltage ΔVthp) than thethreshold voltage Vthp2 of the transistor M2. In other words, thetransistors M1 and M2 may have only slightly different thresholdvoltages Vthp1 and Vthp2 and therefore may be formed in the same processwith only slightly different gate lengths and gate widths.

A voltage lower than that of the node N1 is applied to the node N4 toturn on the transistor M2. Thus, a current flows from the node N1 to thenode N4, and the voltage of the node N3 is made lower than that of thenode N1 by the threshold voltage Vthp2 of the transistor M2 by thediode-connected transistor M2.

In other words, a voltage lower than that of the node N1 by thethreshold voltage Vthp2 of the transistor M2 is applied to the gate ofthe transistor M1. When the voltage Va (input voltage Vin) of a node N2becomes higher than the voltage Vb (output voltage Vout′) of the node N1by the voltage ΔVthp, a potential difference corresponding to thethreshold voltage Vthp1 occurs between the node N2 and the gate of thetransistor M1, and the transistor M1 is turned on. In this manner, therectifier circuit 300 illustrated in FIG. 2A and FIG. 2B may adjust thethreshold voltage Vthp1 of the transistor M1 to a low voltage ΔVthp.

However, during conduction of the transistor M1, the voltage Vgs betweenthe gate and the source of the transistor M1 becomes close to thethreshold voltage Vth of the pMOS transistor. Therefore, the potentialdifference between the nodes N1 and N2 is large, and the conduction lossstill remains as high as, e.g., about 0.3 V at 100 μA.

Below, embodiments of a rectifier circuit and an electronic device willbe described in detail below with reference to the accompanyingdrawings. FIG. 3 is a block diagram illustrating one embodiment of arectifier circuit, and FIG. 4 is a timing chart for explaining theoperation of the rectifier circuit illustrated in FIG. 3. FIG. 5 is adiagram illustrating in close-up a part of the timing chart illustratedin FIG. 4, to explain it in detail, and used to explain the operation ofthe rectifier circuit after the oscillation frequency of an oscillatoris stabilized. A rectifier circuit 100 according to this embodimentrectifies an AC input voltage Vin applied to an input terminal IN andoutputs it from an output terminal OUT as an output voltage Vout.

The rectifier circuit 100 includes an n-channel MOS (nMOS) transistorQ1, a capacitor C1, a control signal generation unit 500, and a boostercircuit 7, as illustrated in FIG. 3. The control signal generation unit500 generates and outputs a control signal SSin to a timing controlcircuit 6, and controls connection and disconnection (ON/OFF) of thenMOS transistor Q1 via the booster circuit 7.

The control signal generation unit 500 includes a reference voltagegenerator 1, an oscillator 2, a comparator 3, a digital timer 4, a pulsegenerator (analog timer) 5, a timing control circuit 6, an inverter I1,a NOR gate NOR1, an OR gate OR1, and an AND gate AND1. NOR1 and OR1function as a switch circuit 8 which performs switching between analogcontrol using a pulse signal PULSE from the pulse generator 5 anddigital control using an output (digital signal) GCTd of the digitaltimer 4, based on an enable signal CEBL.

The nMOS transistor Q1 may be turned on during the period of an AC inputvoltage Vin higher in digital control using the digital signal GCTd thanin analog control using the pulse signal PULSE. The capacitor C1 is usedto smooth the rectified output voltage Vout (VDD) (maintain itconstant).

The nMOS transistor Q1 is placed between the input terminal IN and theoutput terminal OUT, and a gate control signal GCTL boosted by thebooster circuit 7 is input to its control electrode (gate). In otherwords, the transistor Q1 functions as a switch element, undergoes ON/OFFcontrol based on the gate control signal GCTL, and rectifies the ACinput voltage Vin to generate an output voltage Vout. The nMOStransistor Q1 is used as a switch element in this case, so that its sizemay be smaller and a current may be supplied in larger amounts than inthe use of a pMOS transistor. Although a diode D1 is connected betweenthe source and the drain of the transistor Q1, the timing at which thetransistor Q1 is turned on is the highest voltage (peak) portion of theAC input voltage Vin and conduction loss generated by the diode D1 isnegligible, as will be described later.

The pulse generator 5 serves as a circuit which generates a pulse signal(analog pulse) PULSE to turn on the nMOS transistor Q1 during the periodof a possible high AC input voltage Vin (the neighborhood of the highestvoltage). When the rectifier circuit 100 according to this embodiment isapplied to, e.g., an RFID tag (electronic device 150), as long as radiowaves from a reader have a known frequency (e.g., 13.56 MHz), the pulsegenerator 5 generates a signal PULSE corresponding to the radio wavesfrom the reader.

The digital timer 4 receives a clock CLK from the oscillator 2, a powersupply voltage VDD (output voltage Vout), and a signal SS1 output fromthe comparator 3, and generates and outputs an enable signal CEBL and adigital signal GCTd. The digital timer 4 is used to generate a signalfor defining a range (narrow period) closer to the highest AC inputvoltage Vin than the analog pulse PULSE from the pulse generator 5 toimprove the accuracy of the ON period of the nMOS transistor Q1.

The switch circuit 8 performs ON/OFF control of the nMOS transistor Q1by analog control based on the analog pulse PULSE from the pulsegenerator 5, for example, immediately after the startup of a powersupply. The switch circuit 8 further performs ON/OFF control of the nMOStransistor Q1 by switching from the above-mentioned analog control todigital control based on the digital signal (count value) GCTd from thedigital timer 4, for example, after the oscillation frequency of theinternal oscillator 2 is stabilized.

As illustrated in FIG. 4, for example, immediately after the startup ofa power supply, the enable signal CEBL from the digital timer 4 is atlow level “L.” Thus, the output of the switch circuit 8 (OR gate OR1)becomes a signal (PULSE) obtained as the analog pulse PULSE from thepulse generator 5 is inverted twice by the inverter I1 and the NOR gateNOR1.

After the oscillation frequency of the oscillator 2 is stabilized, theenable signal CEBL changes from “L” to high level “H” and the output ofthe switch circuit 8 becomes a digital signal GCTd from the digitaltimer 4 via the OR gate OR1. As a result, the output (control signal)SSin of the AND gate AND1 becomes a signal having the same logic as thatof the output of the switch circuit 8 during the period in which thesignal SS1 output from the comparator 3 is at “H.”

With this operation, the gate control signal GCTL for ON/OFF control ofthe nMOS transistor Q1 acts as a signal based on the analog pulse PULSEimmediately after the startup of a power supply and as a signal based onthe digital signal GCTd after the oscillation frequency of theoscillator 2 is stabilized. In other words, as indicated by Vout in FIG.4, a higher output voltage Vout may be generated after the oscillationfrequency of the oscillator is stabilized than immediately after thestartup of a power supply. FIG. 4 also illustrates an output voltageVout′ generated by the rectifier circuits 200 and 300 described withreference to FIG. 1 to FIG. 2B, for comparison. In other words, with therectifier circuit 100 according to this embodiment, obviously, an outputvoltage Vout higher than the output voltage Vout′ illustrated in FIG. 1to FIG. 2B may be generated not only after the oscillation frequency ofthe oscillator is stabilized, but also immediately after the startup ofa power supply.

The booster circuit 7 receives a delay signal DELAY, a capacitancecontrol signal CTL, and a boosting signal BST from the timing controlcircuit 6, and the power supply voltage VDD (output voltage Vout) andoutputs the boosted gate control signal GCTL to the gate of the nMOStransistor Q1. The booster circuit 7 includes a level shifter 71, aregulator 72, a pMOS transistor Q2, a capacitor C2, inverters 12 and 13,and a diode D2, as illustrated in FIG. 3.

The booster circuit 7 is used to, e.g., raise a signal level of about 2V to about 3 to 4 V that is higher (sufficiently higher) than thethreshold voltage (Vthn) of the nMOS transistor Q1 to reliably turn onthe nMOS transistor Q1 to suppress any conduction loss. The capacitor C2is used to accumulate charges of a signal BOOST output from the inverter13 controlled by the regulator 72 and boost the delay signal DELAY viathe pMOS transistor Q2 to generate a gate control signal GCTL.

The level shifter 71 receives the capacitance control signal CTL, makesa level shift, and generates a capacitance control signal CCTL forON/OFF control of the pMOS transistor Q2. The diode D2 is connectedbetween the source and the drain of the transistor Q2. A boosting signalBOOST is generated using the boosting signal BST via the inverter 12 andthe inverter 13 controlled by the regulator 72. The booster circuit 7illustrated in FIG. 3 is merely an example, and various modificationsand changes may be made, as a matter of course.

As illustrated in FIG. 5, after the oscillation frequency of theoscillator 2 is stabilized (after CEBL changes from “L” to “H”), whenthe AC input voltage Vin exceeds a reference voltage VREF, the signalSS1 output from the comparator 3 changes from “L” to “H.” The timingsignal SSin input to the timing control circuit 6 is a signal based onthe digital signal GCTd from the digital timer 4. The timing controlcircuit 6 generates a delay signal DELAY, a capacitance control signalCTL, and a boosting signal BST using three delay circuits 61 to 63, aswill be described in more detail later with reference to FIG. 10.

The delay signal DELAY is applied to the gate (one end of the capacitorC2) of the nMOS transistor Q1 upon turn-on of the pMOS transistor Q2,boosted by the boosting signal BOOST applied to the other end of thecapacitor C2, and generated as a gate control signal GCTL. The gatecontrol signal GCTL is boosted to a voltage higher than the thresholdvoltage Vthn of the nMOS transistor Q1 to perform ON/OFF control of thetransistor Q1 while reducing the conduction loss upon rectification.

FIG. 6 is a block diagram illustrating one exemplary digital timer inthe rectifier circuit illustrated in FIG. 3, and FIG. 7 is a timingchart for explaining the operation of the digital timer illustrated inFIG. 6. The digital timer 4 receives the clock CLK from the oscillator 2and the signal SS1 from the comparator 3 and generates an enable signalCEBL and a digital signal GCTd.

The digital timer 4 includes flip-flops (FFs) 41, 43, and 44, a counter42, and comparators 45 and 46, as illustrated in FIG. 6. For example, ittakes a certain time for the oscillation frequency of the oscillator 2to stabilize after the startup of a power supply, as described earlier.In view of this, the digital timer 4 includes the function of detectingthat the oscillator has stabilized and outputting an enable signal CEBL,and the function of outputting a digital signal GCTd for generating agate control signal GCTL for the nMOS transistor Q1 by digital control.

The flip-flop 41 captures and holds the signal SS1 input to the D (Data)terminal in accordance with the clock CLK and outputs it from the Qterminal as a signal SS2. The signal SS2 corresponds to a signalobtained by delaying the signal SS1 by one period of the clock CLK, asillustrated in FIG. 7. The signal SS2 is input to the counter 42 andcounted by the clock CLK to generate a count value COUNT and atransition signal EDGE representing the leading edge of the signal SS2.

The count value COUNT and the transition signal EDGE from the counter 42are input to the D terminal and the EN (ENable) terminal of theflip-flop 43. The count value COUNT is also input to the comparator 46and the transition signal EDGE is also input to the EN terminal of theflip-flop 44. In other words, the flip-flop 43 captures and holds thecount value COUNT input to the D terminal in accordance with the clockCLK and outputs it from the Q terminal as a signal B, when thetransition signal EDGE is at “H.”

The signal B from the flip-flop 43 is input to the D terminal of theflip-flop 44 and the comparator 45. The flip-flop 44 captures and holdsthe signal B input to the D terminal when the last transition signalEDGE is at “H,” in accordance with the clock CLK, and outputs it fromthe Q terminal as a signal A. The comparator 45 receives the signal Afrom the flip-flop 44, together with the signal B from the flip-flop 43,and compares the signals A and B with each other.

The comparator 45 captures and compares the signals A and B with eachother, and sets the enable signal CEBL at “H” when, for example, A=B,A=B+1, or A=B−1. In other words, an input signal SS1 having a certainperiod is counted by the clock CLK from the oscillator 2, count valuesCOUNT before and after one period are compared with each other, and theenable signal CEBL is set at “H” after stabilization is determined whenthe difference in count value falls within the range of ±1. The enablesignal CEBL from the comparator 45 is also input to the comparator 46and compared with the count value COUNT from the counter 42.

The comparator 46 outputs a digital signal GCTd having a predeterminedcount value (e.g., COUNT=2) in a certain cycle of the clock CLK afterthe enable signal CEBL changes to “H.” In other words, FIG. 7illustrates an example in which the enable signal CEBL changes to “H”while the count value COUNT is “2.” The oscillation frequency of theoscillator 2 (CLK frequency) may be set higher to improve the accuracyof control of the nMOS transistor Q1, but it may be set to about eightto 16 times the frequency of the input voltage Vin (e.g., the frequencyof carrier waves from an RFID tag: 13.56 MHz) without any problem. Thedigital timer 4 described with reference to FIG. 6 and FIG. 7 is merelyan example, and various modifications and changes may be made, as amatter of course.

FIG. 8 is a circuit diagram illustrating one exemplary reference voltagegenerator in the rectifier circuit illustrated in FIG. 3. The referencevoltage generator 1 has the function of switching the reference voltageVREF from ½×VDD to ¾×VDD, and includes resistors R11 to R16, a switchSW1, a bandgap reference circuit (BGR) 11, and an operational amplifier12, as illustrated in FIG. 8.

The resistors R11 and R12 are divided so that, for example, a node Nahas a voltage equal to a voltage BGR0 output from the bandgap referencecircuit 11 when the power supply voltage VDD (output voltage Vout)reaches a desired voltage (e.g., 2 V). The switch SW1 is controlled bythe output SCTL of the operational amplifier 12 so that SCTL is set at“L” and ½×VDD is selected when the power supply voltage VDD is 2 V orless, and SCTL is set at “H” and ¾×VDD is selected when VDD is higherthan 2 V.

FIG. 9A and FIG. 9B are diagrams for explaining the operation of acomparator based on the output of the reference voltage generatorillustrated in FIG. 8. FIG. 9A illustrates the comparison operation ofthe comparator 3 when the output (reference voltage) VREF of thereference voltage generator 1 is VREF=½×VDD, and FIG. 9B illustrates thecomparison operation of the comparator 3 when this output is VREF=¾×VDD.The comparator 3 compares the voltage levels of the reference voltageVREF and the input voltage Vin (e.g., the AC voltage generated by a13.56-MHz high-frequency signal) with each other.

For example, ½×VDD is assumed to be selected as a reference voltage VREFwhen the power supply voltage VDD (output voltage Vout) is 2 V or less,as illustrated in FIG. 9A. Further, for example, ¾×VDD is assumed to beselected as a reference voltage VREF when the power supply voltage VDDis higher than 2 V, as illustrated in FIG. 9B.

The comparison between FIG. 9A and FIG. 9B reveals that the ON time ofthe pulse signal PULSE may be brought closer to the highest voltage(peak) of the input voltage Vin when VREF=¾×VDD in FIG. 9B than whenVREF=½×VDD in FIG. 9A. In other words, raising VREF when VDD (Vout)becomes equal to or higher than a certain level allows the comparator 3to output a signal SS1 by approximation to the peak of Vin to set theoutput voltage Vout (VDD) higher.

The reference voltage generator 1 described with reference to FIG. 8 toFIG. 9B may switch the reference voltage VREF between two voltagelevels: ½×VDD and ¾×VDD, but it is not limited to such an example. Inother words, VREF may even be switched among, e.g., four voltage levels:½×VDD, ⅝×VDD, ¾×VDD, and ⅞×VDD, based on the voltage level of VDD.

FIG. 10 is a circuit diagram illustrating one exemplary timing controlcircuit in the rectifier circuit illustrated in FIG. 3. The timingcontrol circuit 6 includes three delay circuits 61 to 63 which receivethe control signal SSin (the output of the AND gate AND1) and generate adelay signal DELAY, a capacitance control signal CTL, and a boostingsignal BST, as illustrated in FIG. 10. The delay circuit 61 includesinverters 611, 612, 616, and 617, a resistor 613, a diode 614, and acapacitor 615. The delay circuit 62 includes inverters 621, 622, 626,and 627, a resistor 623, and a capacitor 625. The delay circuit 63includes inverters 631, 636, 637, and 638, a resistor 633, a diode 634,and a capacitor 635.

The delay circuits 61 to 63 form filters using the resistors 613, 623,and 633 and the capacitors 615, 625, and 635, respectively, to adjustthe delay times using the time constants of the filters. In the delaycircuits 61 and 63, the diodes 614 and 634 are connected in parallel tothe resistors 613 and 633 to allow the delay signal DELAY and theboosting signal BST to delay only at the leading edges. In the delaycircuit 62, the values of the resistor 623 and the capacitor 625 are setto delay both the leading and trailing edges of the capacitance controlsignal CTL to obtain respective desired delay times. The configurationof the timing control circuit 6 is not limited to that illustrated inFIG. 10, either, as a matter of course.

FIG. 11 is a block diagram illustrating one exemplary electronic deviceto which one embodiment of a rectifier circuit is applied, andillustrates one exemplary RFID tag. The RFID tag 150 includes an antenna(coil) 151, the rectifier circuit 100 of the above-described embodiment,a shunt circuit 152, a demodulator circuit 153, a modulator circuit 154,a clock generator circuit 155, a logic circuit 156, and a memory circuit157, as illustrated in FIG. 11. The RFID tag 150 may include varioussensors, including, e.g., a temperature sensor and a humidity sensor,store data from the sensors in the memory circuit 157, and send the datain response to requests from a reader-writer (reader).

The RFID tag 150, for example, receives via the antenna 151, ahigh-frequency (RF) signal emitted by the reader-writer and inputs an ACsignal (input voltage Vin) from the terminals RF+ and RF− of the antenna151 to the rectifier circuit 100. In other words, the input voltage Vinis a voltage based on radio waves emitted by the reader (reader-writer).The rectifier circuit 100 converts an AC input voltage Vin into a DCvoltage (an output voltage Vout or a power supply voltage VDD) andcontrols the power supply voltage VDD at a certain level using the shuntcircuit (shunt regulator) 152, as described above.

The power supply voltage VDD stabilized by the shunt circuit 152 isapplied to, e.g., the demodulator circuit 153, the modulator circuit154, the clock generator circuit 155, the logic circuit 156, and thememory circuit 157, which perform respective predetermined operations.In other words, the demodulator circuit 153 demodulates a signalreceived from the antenna 151 (RF+, RF−), operates the logic circuit 156in accordance with a clock generated by the clock generator circuit 155,and performs read/write of the memory circuit 157. The modulator circuit154 is used to, e.g., modulate the data held in the memory circuit 157and send the data to the reader-writer via the antenna 151.

The rectifier circuit 100 according to this embodiment is not limited toapplication to the RFID tag 150 illustrated in FIG. 11, and is widelyapplicable to various electronic devices involving low powerconsumption, including, e.g., noncontact IC cards.

All examples and conditional language provided herein are intended forthe pedagogical purposes of aiding the reader in understanding theinvention and the concepts contributed by the inventor to further theart, and are not to be construed as limitations to such specificallyrecited examples and conditions, nor does the organization of suchexamples in the specification relate to a showing of the superiority andinferiority of the invention. Although one or more embodiments of thepresent invention have been described in detail, it should be understoodthat the various changes, substitutions, and alterations could be madehereto without departing from the spirit and scope of the invention.

What is claimed is:
 1. A rectifier circuit comprising a switch element,which controls connection and disconnection of an AC input voltage usingthe switch element to generate an output voltage, wherein the switchelement comprises an n-channel MOS transistor, and the rectifier circuitfurther comprises: a booster circuit configured to generate and apply agate control signal including a voltage higher than a threshold voltageof the n-channel MOS transistor to a gate of the n-channel MOStransistor; and a control signal generation unit configured to generateand output a control signal for controlling connection and disconnectionof the n-channel MOS transistor to the booster circuit, and establishesconnection to the switch element at a peak portion of the input voltage.2. The rectifier circuit according to claim 1, wherein the controlsignal generation unit comprises: a pulse generator configured togenerate an analog pulse; an oscillator configured to generate a clock;and a digital timer configured to generate a digital signal based on theclock.
 3. The rectifier circuit according to claim 2, wherein thecontrol signal generation unit further comprises: a timing controlcircuit configured to receive the output voltage and the control signal,generate a signal by delaying the control signal, and output thegenerated signal to the booster circuit.
 4. The rectifier circuitaccording to claim 2, wherein the control signal generation unit furthercomprises: a reference voltage generator configured to generate areference voltage; and a comparator configured to compare the inputvoltage with the reference voltage, the pulse generator generates theanalog pulse based on the output voltage and a signal output from thecomparator, and the digital timer generates the digital signal based onthe output voltage and the signal output from the comparator, togetherwith the clock.
 5. The rectifier circuit according to claim 4, whereinthe digital timer further generates an enable signal for definingwhether the control signal is to be generated based on the analog pulseor based on the digital signal.
 6. The rectifier circuit according toclaim 5, wherein the control signal generation unit further comprises: aswitch circuit configured to perform switching to generate the controlsignal based on the analog pulse immediately after startup of a powersupply and generate the control signal based on the digital signal afteran oscillation frequency of the oscillator is stabilized, based on theenable signal.
 7. The rectifier circuit according to claim 6, whereinthe n-channel MOS transistor is connected in a portion closer to a peakof the input voltage in digital control based on the digital signal thanin analog control based on the analog pulse.
 8. The rectifier circuitaccording to claim 7, wherein the digital timer comprises: a counterconfigured to count the clock generated by the oscillator, and generatethe digital signal based on a count value obtained by the counter. 9.The rectifier circuit according to claim 4, wherein the referencevoltage generator generates the reference voltage by switching betweendifferent voltage levels.
 10. The rectifier circuit according to claim9, wherein the reference voltage generator generates the referencevoltage by switching to a voltage level closer to the output voltagewith an increase in the output voltage.
 11. The rectifier circuitaccording to claim 1, wherein the booster circuit generates the gatecontrol signal based on the output voltage and a signal generated bydelaying the control signal.
 12. The rectifier circuit according toclaim 1, wherein the rectifier circuit further comprises: a capacitorconfigured to smooth the output voltage.
 13. An electronic devicecomprising a rectifier circuit including a switch element, configured tocontrol connection and disconnection of an AC input voltage using theswitch element to generate an output voltage, wherein the switch elementincludes an n-channel MOS transistor, and the rectifier circuit furtherincludes: a booster circuit configured to generate and apply a gatecontrol signal including a voltage higher than a threshold voltage ofthe n-channel MOS transistor to a gate of the n-channel MOS transistor;and a control signal generation unit configured to generate and output acontrol signal for controlling connection and disconnection of then-channel MOS transistor to the booster circuit, and establishesconnection to the switch element at a peak portion of the input voltage.14. The electronic device according to claim 13, wherein the electronicdevice comprises an RFID tag, and the input voltage comprises a voltagebased on a radio wave emitted by a reader.